• Publications
  • Influence
RT-Level ITC'99 Benchmarks and First ATPG Results
TLDR
A suite of RT-level benchmarks that help improve research in high-level ATPG tools are proposed and first results on the benchmarks obtained with the prototype tool show the feasibility of the approach.
Fully automatic test program generation for microprocessor cores
TLDR
This paper presents a new approach to automatic test program generation exploiting an evolutionary paradigm that overcomes the main limitations of previous methodologies and provides significantly better results.
Automatic test program generation: a case study
TLDR
This work focuses on simulation-based design validation performed at the behavioral register-transfer level, where designers typically write assertions inside hardware description language (HDL) models and run extensive simulations to increase confidence in device correctness.
Low power BIST via non-linear hybrid cellular automata
TLDR
This paper proposes an algorithm to design a test pattern generator based on cellular automata for testing combinational circuits that effectively reduces power consumption while attaining high fault coverage and experimental results show that this approach reduces the power consumed during test by 34% on average.
On the test of microprocessor IP cores
TLDR
A method for the generation of effective programs for the self-test of a processor that can be partially automated and combines ideas from traditional functional approaches and from the ATPG field is described.
MicroGP—An Evolutionary Assembly Program Generator
  • Giovanni Squillero
  • Computer Science
    Genetic Programming and Evolvable Machines
  • 1 September 2005
This paper describes μGP, an evolutionary approach for generating assembly programs tuned for a specific microprocessor. The approach is based on three clearly separated blocks: an evolutionary core,
Automatic test program generation for pipelined processors
TLDR
A methodology to automatically induce a test program for a microprocessor maximizing a given verification metric is presented, exploiting a new evolutionary algorithm close to Genetic Programming, able to cultivate effective assembly-language programs.
A real-time evolutionary algorithm for Web prediction
TLDR
A new method to exploit user navigational path behavior to predict, in real-time, future requests and adopt a predictive user model based on finite state machines together with an evolutionary algorithm that evolves a population of FSMs for achieving a good prediction rate.
An RT-level fault model with high gate level correlation
TLDR
This paper aims at exploiting the capabilities of VHDL simulators to compute faulty responses at the RT-level, and shows that simulation of a faulty circuit is no more costly than simulation of the original circuit.
High-level observability for effective high-level ATPG
TLDR
Experimental results show how sharp observability metrics are crucial for making effective RT- level ATPG possible: test sequences generated at RT-level outperform commercial gate-level ATPGs on some ITC99 benchmark circuits.
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