• Publications
  • Influence
RT-Level ITC'99 Benchmarks and First ATPG Results
TLDR
New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. Expand
  • 423
  • 40
Automatic test program generation: a case study
TLDR
We focus on simulation-based design validation performed at the behavioral register-transfer level. Expand
  • 135
  • 5
  • PDF
Fully automatic test program generation for microprocessor cores
TLDR
This paper presents a new approach to automatic test program generation exploiting an evolutionary paradigm. Expand
  • 99
  • 5
  • PDF
Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
TLDR
This paper presents a simulation-based methodology for the automatic completion and refinement of verification test sets during the microprocessor design. Expand
  • 14
  • 5
Low power BIST via non-linear hybrid cellular automata
TLDR
In the last decade, researchers devoted much effort to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. Expand
  • 144
  • 4
MicroGP—An Evolutionary Assembly Program Generator
  • Giovanni Squillero
  • Computer Science
  • Genetic Programming and Evolvable Machines
  • 1 September 2005
TLDR
This paper describes μGP, an evolutionary approach for generating assembly programs tuned for a specific microprocessor. Expand
  • 60
  • 4
An RT-level fault model with high gate level correlation
TLDR
This paper focuses on fault simulation at the RT-level, and aims at exploiting the capabilities of VHDL simulators to compute faulty responses. Expand
  • 40
  • 4
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Automatic test program generation for pipelined processors
TLDR
The continuous advances in microelectronics design are creating a significant challenge to design validation in general, but tackling piplined microprocessors is remarkably more demanding. Expand
  • 40
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High-level observability for effective high-level ATPG
TLDR
This paper focuses on observability, one of the open issues in high-level test generation. Expand
  • 32
  • 4
A real-time evolutionary algorithm for Web prediction
TLDR
We propose a new method to exploit user navigational path behavior to predict, in real-time, future requests. Expand
  • 32
  • 4