Giovanni Fiorenza

Learn More
Computer hardware components have changed significantly since the 1960’s, 1970’s, 1980’s, and even since the early 1990’s. All work concerning Rent’s Rule prior to the present paper has been based on a 1971 interpretation of two unpublished memoranda written in 1960 by E. F. Rent at IBM, even though today’s computer components are significantly different(More)
Research on Rent’s rule in electrical engineering, the applied sciences, and technology has been based on the publication of a 1971 interpretation of Rent’s memoranda by B. S. Landman and R. L. Russo. Because of the wide impact of Rent’s work and requests from researchers, we present his original memoranda in this paper. We review the impact of Rent’s work(More)
Ultralarge-scale integrated (ULSI) chip design data is needed for an assessment of existing on-chip wirelength distribution models. Data extracted from modern chips such as high-performance microprocessors provide information about actual wirelength requirements in ULSI chip designs. These requirements are compared with wirelength estimates obtained by(More)
We present a statistical framework to address questions that arise in general problems involving collaboration of several contributors. One instance of this problem occurs in the complex process of designing ultralarge-scale-integration (ULSI) semiconductor chips. In these processes, computeraided design tools are treated as “black boxes.” In most cases,(More)
This paper presents a comprehensive assessment of interconnect requirements in ULSI control logic circuitry and quantifies the agreement observed (1) between estimates and measurements of average wire-length in individual designs in real chips, and (2) between wire-length distributions provided by the models and wire-length distributions obtained from(More)
Power reduction techniques are a critical issue in the design of today's ULSI chips. This paper is concerned with methods to characterize the capacitive load on the POWER4 on-chip global clock distribution [1], which is a large contributor to the overall chip power dissipation. A characterization of the capacitive load is needed because the contributions of(More)
This paper presents models and a methodology to evaluate tradeoffs between technology and design to obtain the highest frequency in ULSI design projects and quantifies the performance improvement that can be expected. With respect to the standard chip design process, it is well known in the academic community that circuits and chips are required to satisfy(More)
  • 1