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The purpose of this paper is to propose a design technique for improving the resistance of the Quasi Delay Insensitive (QDI) Asynchronous logic against Differential Power Analysis Attacks. This countermeasure exploits the properties of the QDI circuit acknowledgement signals to introduce temporal variations so as to randomly desynchronize the data(More)
This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an Asynchronous Analog-to-Digital Converter (A-ADC) is tackled. Its principle is based on a non-uniform sampling scheme and asynchronous technology, that allow significant activity and power savings. A(More)
This work is a contribution to a drastic change in standard signal processing chains: Analog-to-Digital Converters (ADCs), digital processing circuits, Digital-to-Analog Converters (DACs)… Integrated Smart Devices and Communicating Objects are the important applications targeted by this study. The main objective is to reduce their power consumption by one(More)
With a basic CMOS imager, it is impossible to encode the High Dynamic Range (HDR) of natural scenes due to several drawbacks: Mainly of them are the limited DR of the pixel and the output limitation due to the quantification of the analog to digital converter (ADC). Many solutions propose to enhanced the input DR or change integration time following the(More)