Gilles Sicard

Learn More
This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an Asynchronous Analog-to-Digital Converter (A-ADC) is tackled. Its principle is based on a non-uniform sampling scheme and asynchronous technology, that allow significant activity and power savings. A(More)
The purpose of this paper is to propose a design technique for improving the resistance of the Quasi Delay Insensitive (QDI) Asynchronous logic against Differential Power Analysis Attacks. This countermeasure exploits the properties of the QDI circuit acknowledgement signals to introduce temporal variations so as to randomly desynchronize the data(More)
We present in this paper a new readout technique designed in order to control the dataflow outgoing from a logarithmic image sensor. It is based on the reduction of the temporal redundancies in the streaming video frames. The main idea is to distribute the sensor into blocks of NxN pixels, then each block generates the mean value of the luminosities signals(More)
This work is a contribution to a drastic change in standard signal processing chains: Analog-to-Digital Converters (ADCs), digital processing circuits, Digital-to-Analog Converters (DACs)… Integrated Smart Devices and Communicating Objects are the important applications targeted by this study. The main objective is to reduce their power consumption by one(More)