Gianluca Piccinini

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— A great interest has been gained in recent years by a new error-correcting code technique, known as " turbo coding, " which has been proven to offer performance closer to the Shannon's limit than traditional concatenated codes. In this paper, several very large scale integration (VLSI) architectures suitable for turbo decoder implementation are proposed(More)
—The use of " turbo codes " has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is required at very low signal-to-noise ratios (SNR). The problem of extracting the best coding gains from these kind of codes has been deeply investigated in the last years. Also the hardware(More)
—The increased leakage, yield inefficiency, process, power supply and temperature variations have significant after-effects on the performance of complex VLSI architectures especially if mapped on Ultra Deep Sub Micron (UDSM) technologies. In this paper we assess the technology trend based on three industrial technologies (90nm, 65nm and 45nm) using a state(More)
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive coding gains, turbo codes have been proposed for several applications, although they suffer a large decoding delay. This paper presents the design of a turbo decoder with high(More)
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class of fanout trees to the so-called bipolar LT-trees, the topology of the optimal fanout tree is found by means of a dynamic programming algorithm. The buffer selection is in turn(More)
One of the most crucial high performance Systems-on-Chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical design static voltage drop analysis, a priori dynamic voltage drop evaluation is the focus of this(More)