Gianluca Giustolisi

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—In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear versus DS relationships in both triode and saturation) is extracted. All the main(More)
In this paper, we present a low-voltage low-dropout voltage regulator (LDO) for a system-on-chip (SoC) application which, exploiting the multiplication of the Miller effect through the use of a current amplifier, is frequency compensated up to 1-nF capacitive load. The topology and the strategy adopted to design the LDO and the related compensation(More)
—This paper discusses the power-supply noise attenu-ation (PSNA) in the frequency domain of four kinds of bandgap voltage reference that represent the basis of typical voltage references. This performance parameter becomes a fundamental design criterion in high-frequency applications where, due to the reduction in the loop gain, spurious signals coming from(More)
—In this communication, we propose a Miller compensation technique for low voltage LDO regulators which makes use of a current amplifier. The analysis shows how to design the compensation network when no voltage buffer is placed between the LDO error amplifier and power device and suggests a low supply voltage circuit topology that allows to compensate with(More)
In this communication, we propose a compensation procedure for LDO regulators which exploits both a current/buffer amplifier Miller compensation and a standard Miller compensation. The analysis shows how to design the compensation network in order to guarantee the stability for all the loading conditions. The results are then used to design a LDO regulator(More)