Ghavam G. Shahidi

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A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS(More)
Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. Chip power has been increasing rapidly, approaching air cool limit. Power limit is transforming CMOS scaling to more of a density driver. As we move to 32 nm(More)
Surface-channel strained-Ge (s-Ge) p-MOSFETs with high-K/metal gate stack and ozone surface passivation are fabricated, for the first time. The channel is ultrathin (∼3–6 nm thick) s-Ge (∼2.2%, biaxial compression) epitaxially grown on a relaxed Si0.56Ge0.44 virtual substrate. Split capacitance–voltage measurements along with quantummechanical simulations(More)
The microelectronics industry is in the process of transitioning from 2D-planar devices to 3D-non-planar (FinFET). In this paper, a metric is developed to assess the impact of scaling and device performance on chip (circuit) power as it is migrated node-to-node. The impact of node migration is assessed at product level as it is moved from 32 nm (2D-planar)(More)
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