Ghavam G. Shahidi

Learn More
A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS(More)
—Surface-channel strained-Ge (s-Ge) p-MOSFETs with high-K/metal gate stack and ozone surface passivation are fabricated, for the first time. The channel is ultrathin (∼3–6 nm thick) s-Ge (∼2.2%, biaxial compression) epi-taxially grown on a relaxed Si 0.56 Ge 0.44 virtual substrate. Split capacitance–voltage measurements along with quantum-mechanical(More)
  • 1