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In this paper, we present a new 8 transistors (8T) design for Static Random Access Memory (SRAM) cell. In this design during write operation one of the inverters of the cell becomes weaker so that changing the stored data in the cell is more likely in write operation. This leads to increase the write ability of the cell. We used one PMOS and one NMOS(More)
—In this paper, we present a new 9T SRAM cell that has good write-ability and improves read stability at the same time. Simulation results show that the proposed design increases Read SNM (RSNM) and Ion/I of f of read path by 219% and 113%, respectively at supply voltage of 300mV over conventional 6T SRAM cell in a 90nm CMOS technology. Proposed design lets(More)
Scaling in Silicon technology, usage of SRAM Cells has been increased to large extent while designing the embedded Cache and system on-chips in CMOS technology. Power consumption, packing density and the speed are the major factors of concern for designing a chip. The consumption of power and speed of SRAMs are some important issues among a number of(More)
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