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This chapter introduces Chess, a retargetable code generation environment for xed-point DSP processors. Chess addresses a range of commercial as well as application-speciic processors, which are increasingly being used for embedded applications in telecommunications, speech and audio processing. Chess is based on a mixed be-havioural/structural processor(More)
This chapter presents a retargetable code generator specialized in the compilation of self-test programs and exploiting new techniques from Constraint Logic Programming CLP. Firstly, w e show h o w CLP can be exploited to improve the software production process especially for retargetable code generation and test generation. CLP combines the declarative(More)
Apphcation Specific Instruction set Processors (A SIPS) are field or mask programmable processors of which the architecture and instruction set are opti-mised to a speci'c application domain. ASIPS offer a high degree of flexibility and are therefore increasingly being used in competitive markets like telecommunications. However, adequate CAD techniques for(More)
Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a high-level synthesis system for integration of real-time signal processing systems on such processor cores.(More)
This paper describes a new and effective approach to register and interconnect optimisation, which is applicable in a dual context : to reduce chip area in high-level synthesis, and to reduce resource load (and thus execution time) in reiargetable code generation. The key idea is to carefu!ly optimise the way in which data is transferred between functional(More)
In this paper, we propose a global assignment theory for " encoding " state graph transformations. A constraint satisfaction framework is proposed that can guarantee necessary and sufficient conditions for a state graph assignment to result in a transformed state graph that is race-free. Performing transformations at the state graph level has the advantage(More)
In this paper, we discuss a <italic>control-flow transformation</italic> called <italic>loop folding</italic>, during the scheduling of register-transfer code for DSP-systems. Loop folding is functionally equivalent to data-path <italic>pipelining</italic>. An iterative loop-folding procedure, implemented in the CATHEDRAL II compiler, is presented. This(More)
In this article, we propose a global assignment theory for encoding state graph transformations. A constraint satisfaction framework is proposed that can guarantee necessary and sufficient conditions for a state graph assignment to result in a transformed state graph that is free of critical races. Performing transformations at the state graph level has the(More)
The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multi-media and consumer electronics industry. A companion paper in this issue [1] presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of(More)