Learn More
Fluctuations in intrinsic linear V<inf>t</inf>, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic &#963;V<inf>T</inf>, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent(More)
Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a(More)
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias.(More)
A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed in this paper. The circuit technique is based on a cascode bridge that maintains the steady-state voltage differences among the terminals of all of the transistors within a range(More)
  • 1