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Network-on-chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile system-on-chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the(More)
—Emerging new technologies like distributed generation , distributed storage, and demand side load management will change the way we consume and produce energy. These techniques enable the possibility to reduce the greenhouse effect and improve grid stability by optimizing energy streams. By smartly applying future energy production, consumption and storage(More)
Streaming applications are often implemented as task graphs, in which data is communicated from task to task over buffers. Currently, techniques exist to compute buffer capacities that guarantee satisfaction of the throughput constraint if the amount of data produced and consumed by the tasks is known at design-time. However, applications such as audio and(More)
—A spectrum analyzer requires a high linearity to handle strong signals, and at the same time a low NF to enable detection of much weaker signals. This is not only important for lab equipment, but also for the spectrum sensing part of cognitive radio, where low cost and integration is at a premium. Often there is a trade-off between linearity and noise:(More)
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: minimizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and(More)
In order to obtain a cost-efficient solution, tasks share resources in a Multi-Processor System-on-Chip. In our architecture, shared resources are run-time scheduled. We show how the effects of Latency-Rate servers, which is a class of run-time schedulers, can be included in a dataflow model. The resulting dataflow model, which can have an arbitrary(More)
—In this paper, we explore the designs of a circuit switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the(More)
The availability of high-level design entry tooling is crucial for the viability of any reconfigurable SoC architecture. This paper presents a graph covering algorithm. The graph covering is done in two steps: template generation and template selection. The objective of template generation step is to extract functional equivalent structures, i.e. templates,(More)
— This paper presents an iterative hierarchical approach to map an application to a parallel heterogeneous SoC architecture at run-time. The application is modeled as a set of communicating processes. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service. This approach is flexible,(More)