Learn More
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676µm 2 and 0.54µm 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology(More)
We present an innovative and comprehensive approach to characterize and model interconnect wire resistance. We have measured Cu wire resistance for fully processed 10 BEOL Cu levels in IBM high performance 65 nm technologies, and analyzed resistance data for multiple wire widths at multiple temperatures. Combined with the SEM cross-section data of a few(More)
  • 1