Gerald Matusiewicz

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This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676µm 2 and 0.54µm 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology(More)
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