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Billion transistor systems-on-chip increasingly require dynamic management of their hardware components and careful coordination of the tasks that they carry out. Diverse real-time monitoring functions assist towards this objective through the collection of important system metrics, such as throughput of processing elements, communication latency, or(More)
In this paper, we describe the design of a heterogeneous island-based network-on-chip to achieve a power-and thermal-aware coherent system. To this end we utilize different management techniques which employ dynamic frequency scaling circuitry and continuous monitoring through power and temperature sensors per node for dynamic control of workloads. Both(More)
Recommended by P.-C. Chung This paper presents a reconfigurable architecture of a lab-on-chip (LoC) microarray device capable to process data either in genotyping or in gene expression applications in a fraction of the time that is required by the usual software methods running on a standard computer. The entire LoC consists of a microfluidics part for the(More)
In this paper, we describe the architecture of an innovative network processor aiming at the acceleration of packet processing in high speed network interfaces and at the tight coupling of low and high level protocols. The proposed design uses only programmable hard-wired components with line rate throughput and is capable of executing protocols and(More)
Todays' highly complex systems-on-chip require highspeed switching interconnects. Advances on signaling technology on the other hand allows the building of high-degree switching fabrics. Buffered crossbars are receiving increasing attention in these areas since they allow efficient high-performance distributed scheduling by decoupling inputs from outputs.(More)
We describe the queue management block of ATLAS I , a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple(More)