George Economakos

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This paper is a continuation of a previous work by the same authors concerning the use of automated high-level synthesis tools for obtaining high-performance FPGA implementations of industrial automation and control algorithms coded as PLC programs. The proposed method is mainly targeting demanding applications requiring lots of numerical computations.(More)
Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year, the introduction of a new language for hardware descriptions, the SystemC C++ class library, initiated a closer relationship between software and(More)
This paper considers the automatic synthesis of systolic architectures from nested loop algorithmic specifications. The high level input is given in the form of uniform dependence loops with unit dependencies and the target architecture is a multidimensional systolic array with unbounded number of cells. A complete methodology for the hardware synthesis of(More)
Modern multiprocessor heterogeneous systems incorporating multiple hardware accelerators on chip have resulted in an excessive increase in the complexity of hardware/software co-design. Designers have now to explore a design space including both per-accelerator architectural parameters as well as inter-accelerator combinations, i.e. different design(More)
Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important when we deal with Digital System Processor (DSP) kernels, as there are demands for even higher clock frequencies and logic densities, which cannot be satisfied(More)