George Economakos

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Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year, the introduction of a new language for hardware descriptions, the SystemC C++ class library, initiated a closer relationship between software and(More)
This paper considers the automatic synthesis of systolic architectures from nested loop algorithmic specifications. The high level input is given in the form of uniform dependence loops with unit dependencies and the target architecture is a multidimensional systolic array with unbounded number of cells. A complete methodology for the hardware synthesis of(More)
This paper presents a methodology for fast and efficient Design Space Exploration during High Level Synthesis. An augmented instance of the design space is studied taking under consideration the effects of both compiler- and architectural-level transformations onto the final datapath. A new gradient-based pruning technique has been developed, which(More)
Modern applications exhibit increased complexity which introduces extra constraints during implementation related to delay, power consumption and silicon area. This problem is even more important when we deal with Digital System Processor (DSP) kernels, as there are demands for even higher clock frequencies and logic densities, which cannot be satisfied(More)
Attribute grammars have been used extensively in every phase of traditional compiler construction. Recently, it has been shown that they can also be effectively adopted to handle scheduling algorithms in high-level synthesis. Their main advantages are modularity and declarative notation in the development of design automation environments. In this paper,(More)
Design space exploration during high-level synthesis targets the computation of those design solutions which form optimal trade-off points. This quest for optimal trade-offs has been focused on studying the impact of various architectural-level parameters during high-level synthesis algorithms, silently neglecting the trade-offs produced from the combined(More)