George E. Bier

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In this paper, the WISQ architecture is described. This architecture is designed to achieve high performance by exploiting new compiler technology and using a highly segmented pipeline. By having a highly segmented pipeline, a very-high-speed clock can be used. Since a highly segmented pipeline will require relatively long pipelines, a way must be provided(More)
Design rules and the problem of design rule checking are introduced. The critical problem of design rule checking is the execution time required to check a complete chip. Proposed solutions try to take advantage of hierarchical aspects of a layout. The algorithm presented in this paper proposes a different approach. Observing that design rule checking is a(More)
This paper examines the effect of contention for a single shared semaphore protecting critical regions in a multiprocessor operating system on system performance as the number of processors increases. A simple queueing model is used to make predictions as a function of the expected <italic>demand</italic> for the semaphore by each processor. Measurements(More)
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