Gennady Feygin

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In a Viterbi decoder, there are two known memory organization techniques for the storage of survivor sequences from which the decoded information sequence is retrieved, namely register exchange method and traceback method. This paper extends previously known traceback approaches describes two new traceback algorithms, and compares various traceback methods(More)
We propose a least-mean square based gain calibration technique of an RF digitally controlled oscillator (DCO) in an all-digital phase-locked loop (ADPLL). The DCO gain of about 12-kHz/least significant bit is subject to process, voltage and temperature variations, but is tracked and compensated in real time. Precise setting of the inverse DCO gain in the(More)
EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality(More)
Two new algorithms for performing arithmetic coding without employing multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst case normalized excess length to under 0.8% versus 1.911% for the previously known best method of Chevion et al. The second algorithm, suitable only for alphabets of less than(More)
Abstract-Two new algorithms for performing arithmetic coding without employing multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst case normalized excess length to under 0.8% vs 1.911% for the previously known best method of Chevion et a/. The second algorithm, suitable only for alphabets of less(More)
This paper presents some recent advances in the architecture for the data compression technique known as Arithmetic Coding. The new architecture employs loop unrolling and speculative execution of the inner loop of the algorithm to achieve a significant speed-up relative to the Q-Coder architecture. This approach reduces the number of iterations required to(More)
A family of multiprocessor architectures implementing the Viterbi algorithm is presented. The family of architectures is shown to be capable of achieving an increase in throughput that is directly proportional to the number of processors when the number of processors is smaller than the constraint length v of the code. The hardware utilization and the depth(More)