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Two new algorithms for performing arithmetic coding without employing multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst case normalized excess length to under 0.8% versus 1.911% for the previously known best method of Chevion et al. The second algorithm, suitable only for alphabets of less than… (More)

In a Viterbi decoder, there are two known memory organization techniques for the storage of survivor sequences from which the decoded information sequence is retrieved, namely register exchange method and traceback method. This paper extends previously known traceback approaches describes two new traceback algorithms, and compares various traceback methods… (More)

A family of multiprocessor architectures implementing the Viterbi algorithm is presented. The family of ar-chitectures is shown to be capable of achieving an increase in throughput that is directly proportional to the number of processors when the number of processors is smaller than the constraint length v of the code. The hardware utilization and the… (More)

- Robert B. Staszewski, Dirk Leipold, Oren Eliezer, Mitch Entezari, Khurram Muhammad, Imran Bashir +27 others
- ISSCC
- 2008

- Jaimin Mehta, Robert B. Staszewski, Oren Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari +12 others
- ISSCC
- 2010

Two new algorithms for performing arithmetic coding without employing multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst case normalized excess length to under 0.8% vs 1.911% for the previously known best method of Chevion et a/. The second algorithm, suitable only for alphabets of less than 12… (More)

- Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall +4 others
- ISCAS
- 1993

A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read pointer traceback technique. The overall design for a 16-qtate, rate 1/2 decoder requires about 26000 transistors and a core area of 8.5 mma in a 1.2 pm two-level metal CMOS technology.… (More)