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In a Viterbi Decoder, there are two known memory organization techniques for the storage of survivor sequences from which the decoded information sequence is retrieved. The register erchange method is the simplest conceptually but suffers from the disadvantage that every bit in the memory must be read and rewritten for each information bit decoded. The… (More)

- Robert B. Staszewski, John L. Wallberg, Chih-Ming Hung, Gennady Feygin, Mitch Entezari, Dirk Leipold
- IEEE Trans. on Circuits and Systems
- 2006

- Gennady Feygin, P. Glenn Gulak, Paul Chow
- Data Compression Conference
- 1993

Two new algorithms for performing arithmetic coding without employing multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst case normalized excess length to under 0.8% versus 1.911% for the previously known best method of Chevion et al. The second algorithm, suitable only for alphabets of less than… (More)

- Gennady Feygin, P. Glenn Gulak
- IEEE Trans. Communications
- 1993

In a Viterbi decoder, there are two known memory organization techniques for the storage of survivor sequences from which the decoded information sequence is retrieved, namely register exchange method and traceback method. This paper extends previously known traceback approaches describes two new traceback algorithms, and compares various traceback methods… (More)

- Gennady Feygin, P. Glenn Gulak, Paul Chow
- IEEE Trans. Signal Processing
- 1993

A family of multiprocessor architectures implementing the Viterbi algorithm is presented. The family of ar-chitectures is shown to be capable of achieving an increase in throughput that is directly proportional to the number of processors when the number of processors is smaller than the constraint length v of the code. The hardware utilization and the… (More)

- Robert B. Staszewski, Dirk Leipold, +30 authors S. Bhatara
- ISSCC
- 2008

- Gennady Feygin, P. Glenn Gulak, Paul Chow
- Data Compression Conference
- 1994

This paper presents some recent advances in the architecture for the data compression technique known as Arithmetic Coding. The new architecture employs loop unrolling and speculative execution of the inner loop of the algorithm to achieve a significant speed-up relative to the Q-Coder architecture. This approach reduces the number of iterations required to… (More)

- David Yeh, Gennady Feygin, Paul Chow
- FCCM
- 1996

- Jaimin Mehta, Robert B. Staszewski, +15 authors Naveen K. Yanduru
- ISSCC
- 2010

- Gennady Feygin, P. Glenn Gulak, Paul Chow
- Inf. Process. Manage.
- 1994

Two new algorithms for performing arithmetic coding without employing multiplication are presented. The first algorithm, suitable for an alphabet of arbitrary size, reduces the worst case normalized excess length to under 0.8% vs 1.911% for the previously known best method of Chevion et a/. The second algorithm, suitable only for alphabets of less than 12… (More)