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Abstrecr-Given a sliceable floorplan and cell sizes, Otten and Stockmeyer [12], [13] presented an algorithm to find an optimal implementation for each cell. We consider a generalized optimal sizing problem on a set of slicing trees related to an adja-cency graph. For computation efficiency, we combine the tree enumeration and sizing procedures in a unified… (More)

We present an efficient technique to reduce the switching activity in a technology-mapped CMOS combinational circuit based on local logic transformations. The transformations consist of adding redundant connections or gates so as to reduce switching activity. We describe simple and efficient procedures, based on logic implication, for identifying the… (More)

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