Gary D. Carpenter

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The PowerPC 405LP system-on-a-chip (SoC) processor, which was developed for high-content, battery-powered application space, provides dynamic voltage-scaling and onthe-fly frequency-scaling capabilities that allow the system and applications to adapt to changes in their performance demands and power constraints during operation. The 405LP operates over a(More)
Commercial Cache-Coherent Non-Uniform Memory Access (ccNUMA) systems often require extensive investments in hardware design and operating system support. A different approach to building these systems is to use Standard High Volume (SHV) hardware and stock software components as building blocks and assemble them together with minimal investments in hardware(More)
We present a novel technique for performing post-silicon timing characterization, i.e., delay fault test and debug, using on-chip delay measurement of critical paths in Integrated Circuits. In Deep Submicron technologies, timing related failures have become a major source of defective silicon, making it imperative to carry out efficient delay fault testing(More)
A 32nm SOI critical path monitor (CPM) that can provide timing measurements to a Digital PLL for dynamic frequency adjustments in the 8-core POWER7+™ microprocessor is described. The CPM calibrates to within 2% of cycle time from nominal to turbo voltages. Its voltage sensitivity is 10mV/bit. It tracks processor temperature sensitivity to within 1.5%(More)
Recently, graphene field-effect transistors (FET) with cutoff frequencies (f(T)) between 100 and 300 GHz have been reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance (g(ds)= dI(ds)/dV(ds)). A crucial figure-of-merit for analog/RF transistors is the intrinsic voltage gain (g(m)/g(ds))(More)