Ganesh Venkataraman

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We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the high redundancy, a mesh architecture offers high tolerance towards variation in the clock skew. However, such a redundancy comes at the expense of mesh wire length and power(More)
1 Introduction We introduce certain conventions and notations that will be used throughout this paper. For any graph G = (V, E) and any subset C ⊆ E of edges, let G\C denote the graph G = (V, E − C). (u → v) G denotes that there is a path from the vertex u to the vertex v in the graph G; ¬(u → v) G denotes that there is no such path. Let α(G, C) = {(u,v) |(More)
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variations. However, previous works based on this technique were limited to unbuffered clock networks and neglected spatial correlations in the experimental validation. In this work, we(More)
To participate as co-receptor in growth factor signaling, heparan sulfate must have specific structural features. Recent studies show that when the levels of 6-O-sulfation of heparan sulfate are diminished by the activity of extracellular heparan sulfate 6-O-endosulfatases (Sulfs), fibroblast growth factor 2-, heparin binding epidermal growth factor-, and(More)
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock tree design algorithm which is driven by the tolerance towards process variations. We consider tolerance to process variation in various stages of clock tree synthesis which(More)
Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3)(More)
  • He Zhou, Sucharita Roy, Edward Cochran, Radouane Zouaoui, Chia Lin Chu, Jay Duffner +16 others
  • 2011
Heparan sulfate proteoglycans (HSPGs) play a key role in shaping the tumor microenvironment by presenting growth factors, cytokines, and other soluble factors that are critical for host cell recruitment and activation, as well as promoting tumor progression, metastasis, and survival. M402 is a rationally engineered, non-cytotoxic heparan sulfate (HS)(More)
The clock distribution network is a key component on any synchronous VLSI design. As techonology moves into the nanometer era, innovative clocking techniques are required to solve the power dissipation and variability issues. Rotary clocking is a novel technique which employs untermi-nated rings formed by differential transmission lines to save power and(More)
— Nanometer VLSI systems demand robust clock distribution network design for increased process and operating condition variabilities. In this paper, we propose minimum clock distribution network augmentation for guaranteed skew yield. We present theoretical analysis results on an inserted link in a clock network, which scales down local skew and skew(More)
Partitioning has been shown to be an effective method for synthesis of low power finite state machines. In this approach, an FSM is partitioned into two or more coupled sub-machines such that most of the time only one of the sub-machines is active. In this paper, we present a GA based approach for simultaneous partitioning and state assignment of finite(More)