Ganapati Srinivasa

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Over the last decade, homogeneous multi-core processors emerged and became the de-facto approach for offering high parallelism, high performance and scalability for a wide range of platforms. We are now at an interesting juncture where several critical factors (smaller form factor devices, power challenges, need for specialization, etc) are guiding(More)
Heterogeneous multicore processors (HMPs), consisting of cores with different performance/power characteristics , have been proposed to deliver higher energy efficiency than symmetric multicores. This paper investigates the opportunities and limitations in using HMPs to gain energy-efficiency. Unlike previous work focused on server systems, we focus on the(More)
—This paper presents HeteroMates, a solution that uses heterogeneous processors to extend the dynamic power/performance range of client devices. By using a mix of different processors, HeteroMates offers both high performance and reduced power consumption. The solution uses core groups as the abstraction that groups a small number of heterogeneous cores to(More)
DRAM has been the technology for computer main memory since Intel released the first commercial DRAM chip (i1103) in 1970. As technology scales and demand for memory performance, it seems DRAM is facing several challenges. Many other memory technologies are anticipated to replace it but none has emerged as a clear winner thus far. In this paper we post the(More)
Data analysis requires new approaches in many domains for evaluating tools and techniques , particularly when the data sets grow large and more complex. Evaluation–as–a– service (EaaS) was coined as a term to represent evaluation approaches based on APIs, virtual machines or source code submission, different from the common paradigm of evaluating techniques(More)
In this paper, an algorithm for efficient network-wide broadcast (NWB) in mobile ad hoc networks (MANETs) is proposed. The algorithm is performed in an asynchronous and distributed manner by each network node. The algorithm requires only limited topology knowledge, and therefore, is suitable for reactive MANET routing protocols. Simulations show that the(More)
Heterogeneous architectures with single-ISA asymmetric cores have the potential to improve both the performance and energy efficiency of software execution by dynamically selecting the most appropriate core type to run each execution thread. In this paper, we propose a trace-based methodology to explore power and performance benefits of single-ISA(More)