Ganapati Srinivasa

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Over the last decade, homogeneous multi-core processors emerged and became the de-facto approach for offering high parallelism, high performance and scalability for a wide range of platforms. We are now at an interesting juncture where several critical factors (smaller form factor devices, power challenges, need for specialization, etc) are guiding(More)
Heterogeneous multicore processors (HMPs), consisting of cores with different performance/power characteristics , have been proposed to deliver higher energy efficiency than symmetric multicores. This paper investigates the opportunities and limitations in using HMPs to gain energy-efficiency. Unlike previous work focused on server systems, we focus on the(More)
—This paper presents HeteroMates, a solution that uses heterogeneous processors to extend the dynamic power/performance range of client devices. By using a mix of different processors, HeteroMates offers both high performance and reduced power consumption. The solution uses core groups as the abstraction that groups a small number of heterogeneous cores to(More)
Data analysis requires new approaches in many domains for evaluating tools and techniques , particularly when the data sets grow large and more complex. Evaluation–as–a– service (EaaS) was coined as a term to represent evaluation approaches based on APIs, virtual machines or source code submission, different from the common paradigm of evaluating techniques(More)
Heterogeneous architectures with single-ISA asymmetric cores have the potential to improve both the performance and energy efficiency of software execution by dynamically selecting the most appropriate core type to run each execution thread. In this paper, we propose a trace-based methodology to explore power and performance benefits of single-ISA(More)
The current usage of client devices - smart phones, tracking devices and wearable electronics - force us to take a deep look at energy consumption, they demand long battery life. Energy needs also get exacerbated by the demands of high level of connectivity, the Always On Always Connected usage model expected of such devices. We are unable to predict the(More)
Peering at the next decade, will explore the processor and platform architecture challenges, as to what areas are undergoing enormous changes, while surveying the learning over the past two decades. While exploring the next decade, will look at the processor internal interconnect evolution along with on chip resources starting with cache, memory controller(More)
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