Gabriele Manganaro

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A 1.8 V 10 b 210 MS/s CMOS pipelined ADC in 0.18 um CMOS process is presented. The low power consumption at high sampling rate is achieved by using an opamp-sharing technique in 2.5 b/stage pipelined ADC architecture. The opamp settling behavior is well controlled through a regulated switch driving scheme. The clever arrangement of capacitor array renders(More)
A continuous-time bandpass ΔΣ modulator (CTBPDSM) is a good solution for software-defined-radio (SDR) since it allows much flexibility in the digital backend and also decreases the complexity of the receiver chain by combining several analog blocks into a single ADC [1]. However, conventional CTBPDSMs suffer from large power consumption and occupy large(More)
A band-pass !" modulator that uses two time interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40-MHz IF provide a signal band of 1 MHz with 72-dB DR and 65.1-dB peak SNR. The circuit, integrated in a 0.18-!m CMOS technology, uses a 60-MHz clock per channel. Experimental results show that the in-band region is(More)