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The classical Steiner tree problem in weighted graphs seeks a minimum weight connected subgraph containing a given subset of the vertices (terminals). We present a new polynomial-time heuristic that achieves a best-known approximation ratio of 1 + ln 3 2 ≈ 1.55 for general graphs, and best-known approximation ratios of ≈ 1.28 for quasi-bipartite graphs(More)
We propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. The approach is based on a new bounded-radius minimum routing tree formulation. We first present several heuris-tics with good performance, based on an analog of Prim's minimum spanning tree construction. Next, we give an algorithm which(More)
Recently Ari Juels suggested a "yoking-proof" where a pair of radio-frequency identification (RFID) tags are both read within a specified time bound, and left open for future research the problem of generating a proof for larger groups of tags. We generalize his protocol by developing a proof which ensures that a group of tags is read within a certain time(More)
We present critical-sink routing tree (CSRT) constructions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and "global slack removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing(More)
Previous literature on the Traveling Salesman Problem (TSP) assumed that the sites to be visited are stationary. Motivated by practical applications, we introduce a time-dependent generalization of TSP which we call Moving-Target TSP, where a pursuer must intercept in minimum time a set of targets which move with constant velocities. We propose approximate(More)
The minimum rectilinear Steiner tree (MRST) problem is very important for such aspects of physical layout as global routing and wiring estimation. Virtually all previous heuristics for computing rectilinear Steiner trees begin with a minimum spanning tree (MST) topology and rearrange edges to induce Steiner points. This paper gives a more direct approach(More)
In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made(More)