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This paper presents an efficient parallel architecture for high-speed maximum a posteriori (MAP) probability detectors. The parallel systolic scheme proposed here builds upon a sliding window approach, and is capable of providing very high throughput. The implementation of an 8-state MAP decoder on an off-the-shelf field programmable gate array (FPGA)(More)
— We present a novel maximum likelihood sequence detection (MLSD) receiver structure for nonlinear channels. This scheme is derived by treating the NLC as a multiple input/multiple output system. Then, orthogonal signal components are computed using a special form of space-time whitened matched filter (ST-WMF) obtained by a modified Gram–Schmidt(More)
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