Gabor Madl

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Key challenges in the performance estimation of distributed real-time embedded (DRE) systems include the systematic measurement of coverage by simulations, and the automated generation of directed test vectors. This paper investigates how DRE systems can be represented as discrete event systems (DES) in continuous time, and proposes an automated method for(More)
Component middleware provides dependable and efficient platforms that support key functional, and quality of service (QoS) needs of distributed real-time embedded (DRE) systems. Component middleware, however, also introduces challenges for DRE system developers, such as evaluating the predictability of DRE system behavior, and choosing the right design(More)
Distributed real-time embedded (DRE) systems often need to satisfy various time, resource and fault-tolerance constraints. To manage the complexity of scheduling these systems many methods use Rate Mono-tonic Scheduling assuming a time-triggered architecture. This paper presents a method that captures the reac-tive behavior of complex time-and event-driven(More)
The ARM Advanced Microcontroller Bus Architecture (AMBA) is a widely used interconnection standard for SoC design. In order to support high-speed pipelined data transfers, AMBA supports a rich set of bus signals, making the analysis of AMBA-based embedded systems a challenging proposition. This paper makes two main contributions to the analysis and(More)
Key challenges in distributed real-time embedded (DRE) system developments include safe composition of system components and mapping the functional specifications onto the target platform. Model-based verification techniques provide a way for the design-time analysis of DRE systems enabling rapid evaluation of design alternatives with respect to given(More)
This paper presents a conservative approximation method for the real-time verification of asynchronous event-driven distributed systems. This problem is known to be undecidable in the generic setting. The proposed approach is based on composable timed automata models that provide a sufficient condition to determine schedulability. We demonstrate the method(More)
—This paper introduces the Cross-abstraction Real-time Analysis (CARTA) framework for the model-based functional verification and performance estimation of chip multiprocessors (CMP) utilizing bus matrix (crossbar switch) interconnection networks. We argue that the inherent complexity in CMP designs requires the syner-gistic use of various models of(More)
Common coupling (sharing global variables across modules) is a metric for software quality, and has been used in studies of maintainability. But when the global variables in question are large data structures, one must decide whether to consider such data structures as complete units, or whether to consider each of their fields individually. We explore this(More)