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Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Abstract—Analog–Digital (A/D)(More)
In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (DeltaSigma) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed.(More)
—A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is proposed. This scheme functions even with large parasitic capacitances(More)
A switched-R-MOSFET-C filter with tunable corner frequency is described. The tunability is achieved by varying the clock duty cycle using an automatic tuning circuit. This tuning method does not involve a change in any gate voltage , and is therefore particularly suitable for low-voltage and high-linearity applications. The advantages of the proposed method(More)
The design and performance of a switched-R-MOSFET-C filter is presented in this paper. The filter achieves -77dB THD using a 0.6V supply, and -90dB THD using a 0.8V supply, with a 0.6Vpp differential 2kHz sine input. High linearity at a low supply voltage is achieved by the use of duty-cycle controlled tuning inside a feedback loop