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A cryptanalytic time-memory tradeoff allows the cryptanal-ysis of any N key symmetric cryptosystem in O(N 2 3) operations with O(N 2 3) storage, if a precomputation of O(N) operations has been done in advance. This procedure is well known but did not lead to any realistic implementations. In this paper, the experimental results for the crypt-analysis of DES… (More)

We present a fast involutional block cipher optimized for re-configurable hardware implementations. ICEBERG uses 64-bit text blocks and 128-bit keys. All components are involutional and allow very efficient combinations of encryption/decryption. Hardware implementations of ICEBERG allow to change the key at every clock cycle without any performance loss and… (More)

(a) Design methodology. (b) Algorithmic optimization. (c) Implementation schemes. (d) Optimal pipeline.

Hardware implementations of the Advanced En-cryption Standard (AES) Rijndael algorithm have recently been the object of an intensive evaluation. Several papers describe efficient architectures for ASICs 1 and FPGAs 2. In this context, the highest effort was devoted to high throughput (up to 20 Gbps) encryption-only designs, fewer works studied low area… (More)

In 1980, Martin Hellman [1] introduced the concept of crypt-analytic time-memory tradeoffs, which allows the cryptanalysis of any N key symmetric cryptosystem in O(N 2 3) operations with O(N 2 3) storage , provided a precomputation of O(N) is performed beforehand. This procedure is well known but did not lead to realistic implementations. This paper… (More)

—In its basic version, linear cryptanalysis is a known-plaintext attack that uses a linear relation between input-bits, output-bits, and key-bits of an encryption algorithm that holds with a certain probability. If enough plaintext-ciphertext pairs are provided, this approximation can be used to assign probabilities to the possible keys and to locate the… (More)

This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique to protect smart card implementations from these attacks. We demonstrate that recent reconfigurable devices offer excellent opportunities to implement a masked… (More)

We propose a new mathematical DES description that allows optimized implementations. It also provides the best DES and triple-DES FPGA implementations known in term of ratio throughput/area, where area means the number of FPGA slices used. First, we get a less resource consuming unrolled DES implementation that works at data rates of 21.3 Gbps (333 MHz),… (More)

This paper presents an updated implementation of the Advanced Encryption Standard (AES) on the recent Xilinx Virtex-5 FP-GAs. We show how a modified slice structure in these reconfigurable hardware devices results in significant improvement of the design efficiency. In particular, a single substitution box of the AES can fit in 8 FPGA slices. We combine… (More)

This paper presents FPGA (Field Programmable Gate Array) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and Encrypt/Decrypt… (More)