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Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications
- G. Rouvroy, François-Xavier Standaert, J. Quisquater, J. Legat
- Computer Science, MathematicsInternational Conference on Information…
- 5 April 2004
This work purpose an efficient solution to combine Rijndael encryption and decryption in one FPGA design, with a strong focus on low area constraints, which fits into the smallest Xilinx FPGAs, deals with data streams of 208 Mbps, and improves by 68% the best-known similar designs in terms of ratio Throughput/Area.
Implementation of the AES-128 on Virtex-5 FPGAs
- P. Bulens, François-Xavier Standaert, J. Quisquater, P. Pellegrin, G. Rouvroy
- Computer ScienceAFRICACRYPT
- 11 June 2008
This paper presents an updated implementation of the Advanced Encryption Standard (AES) on the recent Xilinx Virtex-5 FPGAs. We show how a modified slice structure in these reconfigurable hardware…
An Overview of Power Analysis Attacks Against Field Programmable Gate Arrays
- François-Xavier Standaert, Eric Peeters, G. Rouvroy, J. Quisquater
- Computer Science, MathematicsProceedings of the IEEE
- 23 January 2006
This paper presents recent results of attacks attempted against standard encryption algorithms, provides a theoretical estimation of these attacks based on simple statistical parameters and evaluates the cost and security of different possible countermeasures.
ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware
- François-Xavier Standaert, G. Piret, G. Rouvroy, J. Quisquater, J. Legat
- Computer Science, MathematicsFSE
- 5 February 2004
The resulting design offers better hardware efficiency than other recent 128-key-bit block ciphers and Resistance against side-channel cryptanalysis was also considered as a design criteria for ICEBERG.
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
A rigorous study of the possible implementation schemes, but also proposes heuristics to evaluate hardware efficiency at different steps of the design process and defines an optimal pipeline that takes the place and route constraints into account.
FPGA implementations of the ICEBERG block cipher
A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results
The algorithm proposed decreases the expected number of memory accesses with sensible modifications of the other parameters and allows much more realistic implementations of fast key search machines and solve theoretical open problems of previous models.
A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation
- J. Quisquater, François-Xavier Standaert, G. Rouvroy, J. David, J. Legat
- Computer Science, MathematicsFPL
- 2 September 2002
The experimental results for the cryptanalysis of DES that are presented are based on a time-memory tradeoff using distinguished points, a method which is referenced to Rivest .
FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
- François-Xavier Standaert, G. Rouvroy, J. Quisquater
- Computer ScienceInternational Conference on Field Programmable…
- 1 August 2006
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously introduced technique…
A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL
- François-Xavier Standaert, G. Rouvroy, J. Quisquater, J. Legat
- Computer Science, MathematicsFPGA '03
- 23 February 2003
This report investigates a methodology to efficiently implement block ciphers in CLB-based FPGA's and proposes designs that unroll the 10 AES rounds and pipeline them in order to optimize the frequency and throughput results.