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The influence of different MOS and bipolar device parameters on the switching speed of a BiCMOS buffer is described. This influence is studied by looking at the response of a BiCMOS inverter to a… (More)
Scaling rules for bipolar transistors in BiCMOS gates are derived such that the gates maintain their performance advantage over scaled CMOS implementations. These are compared with those for bipolar… (More)
Simple delay models are derived for the different regions of operation for the bipolar transistors in a BiCMOS driver. The delay equations are approximate but extremely useful in relating the gate… (More)
The BiPMOS device associated with n-well BiCMOS technologies consumes a substantial area for isolation. A merged BiPMOS device structure is introduced to reduce the device size for BiCMOS VLSI. The… (More)
A BiPMOS device based on a 2- mu m BiCMOS technology with a buried layer and a 0.8- mu m 1*10/sup 16/ cm/sup -3/ epilayer is investigated. Conventional one-dimensional models of BiPMOS devices are… (More)
The BiNMOS device associated with 2- mu m n-well BiCMOS technologies consumes substantial area for isolation. A merged BiNMOS device structure is introduced to reduce device size. The performance of… (More)