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A Gaussian Process Surrogate Model Assisted Evolutionary Algorithm for Medium Scale Expensive Optimization Problems
Surrogate model assisted evolutionary algorithms (SAEAs) have recently attracted much attention due to the growing need for computationally expensive optimization in many real-world applications.Expand
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Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies
With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For eachExpand
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Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-$\mu{\hbox {m}}$ Standard CMOS
This paper discusses two antennas monolithically integrated on-chip to be used respectively for wireless powering and UWB transmission of a tag designed and fabricated in 0.18-μm CMOS technology. AExpand
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Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs
The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the pastExpand
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A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators
An approach is presented for the high-level simulation and synthesis of discrete-time /spl Delta//spl Sigma/ modulators based on a simulation-based optimization strategy. The high-level synthesisExpand
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Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits
This paper presents an overview of methods to automatically generate posynomial response surface models for the performance characteristics of analog integrated circuits based on numerical simulationExpand
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Systematic design exploration of delta-sigma ADCs
An algorithm for architecture-level exploration of the /spl Delta//spl Sigma/ A/D converter (ADC) design space is presented. Starting from the desired specification, the algorithm finds an optimalExpand
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A remote-powered RFID tag with 10Mb/s UWB uplink and −18.5dBm sensitivity UHF downlink in 0.18µm CMOS
Wireless sensing and positioning are new added functions, highly demanded, in future and emerging RFID technology [1]. The data rate of existing passive RFID tags is limited to a few hundreds of kb/sExpand
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Generalized posynomial performance modeling
This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. The coefficient set as well as theExpand
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Efficient multiobjective synthesis of analog circuits using hierarchical Pareto-optimal performance hypersurfaces
An efficient methodology is presented to generate the Pareto-optimal hypersurface of the performance space of a complete mixed-signal electronic system. This Pareto-optimal front offers the designerExpand
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