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Optimized Java Binary and Virtual Machine for Tiny Motes
TakaTuka’s optimization of program memory usage is focused on, which optimizes storage requirements for the Java classfiles as well as for the JVM interpreter, both of which are expected to be stored on the embedded devices.
KIV: overview and VerifyThis competition
- G. Ernst, J. Pfähler, G. Schellhorn, Dominik Haneberg, W. Reif
- Computer ScienceInternational Journal on Software Tools for…
- 1 November 2015
The KIV verification system and its latest additions are described and the solutions to the three VerifyThis problems are discussed and which features of KIV were used in solving them.
Introducing TakaTuka: a Java virtualmachine for motes
- Faisal Aslam, C. Schindelhauer, G. Ernst, Damian Spyra, Jan Meyer, M. Zalloom
- Computer ScienceSenSys '08
- 5 November 2008
TakaTuka, a tiny Java Virtual Machine (JVM) for wireless sensor motes, is presented and the preliminary version successfully runs on Crossbow's mica2 motes.
Verification of a Virtual Filesystem Switch
This paper bridges the gap between an abstract specification of POSIX and a realistic model of VFS by ASM refinement by considering hard-links, file handles and the partitioning of file content into pages.
Two-Layered Falsification of Hybrid Systems Guided by Monte Carlo Tree Search
- Zhenya Zhang, G. Ernst, Sean Sedwards, Paolo Arcaini, I. Hasuo
- Computer ScienceIEEE Transactions on Computer-Aided Design of…
- 16 March 2018
A two-layered optimization framework that uses Monte Carlo tree search (MCTS), a popular machine learning technique with solid mathematical and empirical foundations, that guides the lower layer of local hill-climbing optimization, thus balancing exploration and exploitation in a disciplined manner.
ARCH-COMP 2019 Category Report: Falsification
The main outcome of the 2019 ARCH workshop for the falsification of temporal logic specifications over Cyber-Physical Systems is a common benchmark repository, and an initial base-line for falsification, with results from multiple tools, which will facilitate comparisons and tracking of the state-of-the-art in falsification in the future.
SecCSL: Security Concurrent Separation Logic
This work presents SecCSL, a concurrent separation logic for proving expressive, data-dependent information flow security properties of low-level programs, and implements SecC, an automatic verifier for a subset of the C programming language, which is applied to a range of benchmarks.
Interleaved Programs and Rely-Guarantee Reasoning with ITL
- G. Schellhorn, B. Tofan, G. Ernst, W. Reif
- Computer ScienceEighteenth International Symposium on Temporal…
- 12 September 2011
A logic that extends basicITL with explicit, interleaved programs, by integrating the logic with higher-order logic, adding recursive procedures and rules to reason about fairness and showing how rules for rely-guarantee reasoning can be derived.
Development of a Verified Flash File System
This paper gives an overview over the development of a formally verified file system for flash memory based on Abstract State Machines and incremental modular refinement and draws preliminary conclusions on the methodology and the required tool support.
ARCH-COMP 2020 Category Report: Falsification
The 2020 friendly competition in the ARCH workshop for the falsification of temporal logic specifications over Cyber-Physical Systems has two new participating tools with novel approaches, and the results show a clear improvement over previous performances on some benchmarks.