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High aspect ratio TSV copper filling with different seed layers
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed layer nature on filling ratio and void formation will be discussed withExpand
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Assembly and reliability of flip chip solder joints using miniaturized Au/Sn bumps
Flip chip assembly experiments using small electroplated Au/Sn bumps, i.e. bumps of 50 /spl mu/m in diameter and less, are carried out. After plating the bumps consist of a Au layer with a thinner SnExpand
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Precise flip chip assembly using electroplated AuSn20 and SnAg3.5 solder
In order to reduce costs in packaging especially for optoelectronic devices technologies are desirable that enable precise assembly at low cost. A flip chip assembly approach is presented using theExpand
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Nanoscale decoration of electrode surfaces with an STM
Abstract The tip of a scanning tunnelling microscope (STM) has been used to deposit nanometer-sized clusters of copper or silver on bare and thiol-covered gold electrode surfaces at predeterminedExpand
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Effect of the Cu thickness on the stability of a Ni/Cu bilayer UBM of lead free microbumps during liquid and solid state aging
The present study focuses on liquid and solid phase reactions between an electrodeposited bilayer UBM and Sn, which is chosen as worst case solder material for lead free bumping. Small sized bumpsExpand
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Tip-Induced Formation of Nanometer-Sized Metal Clusters*
The tip of a scanning tunneling microscope has been used to deposit nanometer-sized copper and palladium clusters on flat gold electrode surfaces at predetermined positions. This allows theExpand
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Development and evaluation of lead free reflow soldering techniques for the flip chip bonding of large GaAs pixel detectors on Si readout chip
Lead free reflow soldering techniques applying AuSn as well as SnAg electroplated bumps were chosen for the evaluation of the flip chip bonding process for a x-ray pixel detector. Both can be used inExpand
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W-band flip-chip VCO in thin-film environment
A flip-chip packaging approach for W-band GaAs chips is presented using thin-film structures on silicon as carrier substrate. Reliability investigations indicate that, depending on bump size, the CTEExpand
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Development and fabrication of a thin film thermo test chip and its integration into a test system for thermal interface characterization
This paper deals with the development und fabrication of a thermal test chip (TTC) to be used for thermal characterisation and qualification of materials and packages. The TTC is designed as aExpand
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Copper filling of TSVs for interposer applications
For the electrochemical filling of through silicon vias (TSVs) the geometry of these vias as well as their quantity on the wafer have a severe influence on the electrochemical process parameters, inExpand
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