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Universal schemes for parallel communication
In this paper we isolate a combinatorial problem that, we believe, lies at the heart of this question and provide some encouragingly positive solutions to it. Expand
400 Gb/s Programmable Packet Parsing on a Single FPGA
Packet parsing is necessary at all points in the modern networking infrastructure, to support packet classification and security functions, as well as for protocol implementation. Expand
A Virtual Hardware Operating System for the Xilinx XC6200
This paper explores ways in which the flexibility and rapid reconfigurability of FPGA hardware can be harnessed in an effective way by conventional processormemory subsystems. Expand
Networking on chip with platform FPGAs
  • G. Brebner, Delon Levi
  • Computer Science
  • Proceedings. IEEE International Conference on…
  • 15 December 2003
This paper is concerned with networking at the chip level. Expand
The P4->NetFPGA Workflow for Line-Rate Packet Processing
We developed the P4->NetFPGA workflow, allowing developers to describe how packets are to be processed in the high-level P4 language, then compile their P4 programs to run at line rate on the NetFPGA SUME board. Expand
The swappable logic unit: a paradigm for virtual hardware
  • G. Brebner
  • Computer Science
  • Proceedings. The 5th Annual IEEE Symposium on…
  • 16 April 1997
This paper looks in some detail at how SLUs will fit within the overall environment of a fairly conventional hardware/software system. Expand
Chip-Based Reconfigurable Task Management
Modularity is a key aspect of system design, particularly in the era of system-on-chip. Expand
High-Speed Packet Processing using Reconfigurable Computing
This paper presents a tool chain that maps a domain-specific packet-processing language called PX to high-performance reconfigurable-computing architectures based on field-programmable gate array (FPGA) technology. Expand
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems
This paper presents the OpenDF framework and recalls that dataflow programming was once invented to address the problem of parallel computing. Expand
Whippersnapper: A P4 Language Benchmark Suite
We propose Whippersnapper, a set of benchmarks for P4, a benchmark suite that addresses these challenges. Expand