Learn More
Battery lifetime, a primary design constraint for mobile embedded systems, has been shown to depend heavily on the load current profile. This paper explores how scheduling guidelines from battery models can help in extending battery capacity. It then presents a 'battery-aware scheduling' methodology for periodically arriving task graphs with real time(More)
With increasing interest in sophisticated graphics capabilities in mobile systems, energy consumption of graphics hardware is becoming a major design concern in addition to the traditional performance enhancement criteria. Among the different steps in the graphics processing pipeline, we have observed that memory accesses during texture mapping -- a highly(More)
In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGSThomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for(More)
Design of a 3.3V comaptible 2.5V TTL-toCMOS bidirectional I/O buffer is proposed. Gate oxide protectiom was implemented without active voltage degradation, which reduces static and dynamic current levels and improves noise immunity for the low voltage circuit of this kind. Fast removal of stored charge further improve gate oxide protection and circuit(More)
The representation of images is a fundamental issue. Wavelet transform is the foundation on which the state of the art still-image compression algorithms are based. These algorithms exploit good energy compaction property of wavelet representation. In this work we propose a new paradigm in the wavelet based image representation. The proposed work uses the(More)
A low Vmin, 6T-SRAM is realized in 28nm UTBB (Ultra-Thin Body and BOX) FDSOI technology using read and write assist methods. We could reduce the Vmin of SRAM cell to 0.5V for the 0.120um2 high density 6T-SRAM. Read margin of the SRAM cell is recovered using a compensated under driven word line scheme. Write assist is realized using negative bit-line(More)