G. Mareswara Rao

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In this paper, a novel low power pulsed flip-flop (P-FF) design featuring a sleep transistor scheme is proposed. In order to improve the leakage robustness for sub-90nm low clock load dynamic flip-flops, a novel sleep transistor scheme is proposed. The scheme is implemented using CMOS 90nm technology file in Synopsis HSPICE. As compared to the conventional(More)
Under a deregulated environment, electricity consumers and suppliers generally establish various bilateral power transactions/contracts. The transmission company normally honors and executes these bilateral contracts as far as the system design and operating conditions permit. This paper describes determination of optimal bilateral contracts by using line(More)
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