G. M. Paulzen

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Hot-carrier-induced interface-trap generation in NMOSFET's is a serious reliability hazard for CMOS circuits. Its prediction has been either inaccurate or it needed many process dependent fitting parameters. We introduce a new method that improves lifetime prediction by orders of magnitude. Our method requires no additional fitting parameter and is(More)
For a 0.25 &#x03BC;m CMOS process a simple and compatible two-step N<sub>2</sub>O nitridation technology was developed. High quality dielectrics were obtained for both surface channel PMOS and NMOS devices. The use of the nitridation technology improves the gate oxide quality considerably. Furthermore the technology enables the use of(More)
A new stand-alone diode programmable read only memory (DPROM) technology for one-time-programmable memories is presented. The technology features small cell size and low mask count. The memory function is based on the formation of a diode-antifuse by gate oxide breakdown. The functionality of DPROM circuits is demonstrated and the program, read and(More)
The Large-Angle-Tilted-Implanted-Drain structure (LATID) has been shown to alleviate hot-carrier induced degradation in NMOSFETs. In a comparison of conventional drain, LDD and several different 0.35 &#x03BC;m LATID NMOSFETs we show that a reduced avalanche multiplication factor and a reduced influence of the generated interface states contribute to this(More)
The device design, fabrication and characterisation of NMOS and PMOS transistors of a 0.25 &#x003BC;m CMOS technology will be discussed. The devices were optimized for a reduced power supply voltage of 2.5 V. High quality devices with good control of short channel effects were obtained. Hot carrier degradation experiments showed that NMOS devices could(More)
A new hot-carrier degradation mechanism becomes important in 0.25 /spl mu/m PMOSFET's. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many(More)
We report on the design, manufacturing and performance of NMOS transistors optimised or an effective channel length of 0.13 &#x003BC;m. The influence of the gate oxide thickness and pocket implants to device performance was studied. Pocket implanted devices show a high drive current (530 &#x003BC;A/&#x003BC;m at 1.8 V) and low off-current, with good(More)
A 0.3 &#x003BC;n CMOS process with an advanced LOCOS field isolation in combination with optimized I-line photolithography is described. High device performance maintaining low off-state leakage currents were obtained using retrograde well technology in combination with shallow junction drain extension devices. The key process technology is the improved(More)