G. Fleishon

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We describe the optimization of a 55 V breakdown LDMOS embedded in a 0.18 micron based power management platform. The devices self aligned structure allow the accessing low RdsOn values of 50 mohm mm<sup>2</sup>. We focus on the effects of gate poly over STI overlap which can increase the breakdown voltage by 10 V and reduce maximum substrate current 5 fold(More)
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