G. Fiannaca

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Wafer level accelerated testing is a key tool to perform fast reliability assessment of new technologies. This paper presents an innovative methodology developed to perform accurate life-time extrapolation of 3-dimensional (3D) high density capacitors through Constant Electric field Stress (CES) test. This methodology is first based on dielectric thickness(More)
The aim of this work is to determine a joule heating prediction model for thick copper/Low-k interconnects on glass substrate technology. Experiments and simulations have been used to define thermal conductivities of our stack material from thermal resistance study. In a second time, the thermal resistance is used as quantitative response to predict the(More)
The aim of this work is to define a joule heating prediction tool under DC stress for thick copper/Low-k inductors on glass substrate technology. The thermal resistance experimental results have been approximated by an empirical model and, combined with thermal coefficient of resistance formalism; allow us to define an analytical temperature joule heating(More)
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