G. Chabanne

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A new CMP-less integration approach for highly scaled totally silicided (TOSI) gate bulk transistors based on the use of selective S/D Si epitaxy and ultra-low gates " , Solid-State Electronics 50, n°4, pp. 620-626, 2006. tuning through dopant scanning and related effects in nickel fully silicided (FUSI/TOSI) gate for sub-45nm nodes CMOS " , IEDM Technical(More)
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