Götz Kappen

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In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in low-power, low-cost SoC for multioperable GNSS positioning is described, featuring sufficient computational power and flexibility. The central processing unit of the reconfigur-able hardware macro is an ASIP accelerated by additional eFPGA and weakly(More)
This paper presents the enhancement of an ASIP's floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications and subsequent adaptation of software development tools (e.g. assembler, linker and compiler) are described. Additionally, this work focuses on seamless integration of the co-processor(More)
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