Götz Kappen

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In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in low-power, low-cost SoC for multioperable GNSS positioning is described, featuring sufficient computational power and flexibility. The central processing unit of the reconfigurable hardware macro is an ASIP accelerated by additional eFPGA and weakly(More)
—This paper presents the conceptual design of a compact 2x2 array receiver for GNSS applications. Besides mere miniaturization, the goal of this work is also investigation on novel techniques for coping with the strong mutual coupling imposed in electrically small antenna arrays and RF front ends, by means of eigenmode reception and digital beamforming in(More)
BIOGRAPHY Götz KAPPEN received the Dipl.-Ing. degree in 2002 from RWTH Aachen University. Since then he has been working as a PhD student at the Chair of Electrical Engineering and Computer Systems, RWTH Aachen University. His fields of research are satellite navigation systems and digital signal processing. Lothar KURZ recently received the Dipl.-Ing.(More)
This paper presents an architecture for an embedded multi-antenna digital GNSS receiver. A two-stage adaptive beamformer for interference suppression and Line-of-Sight (LoS) signal amplification is presented and analyzed w.r.t. to an efficient implementation on embedded receivers. Jammer signals are mitigated at pre-correlation stage whereas the LoS signals(More)
Application-specific reconfigurable processor architectures provide a remarkable potential for systems which achieve concurrently high performance, area efficiency, energy efficiency, run-time adaptivity, and sufficient flexibility. Thus, they represent competitive design alternatives that provide significant improvements in some of these figures of merit(More)
This paper presents the enhancement of an ASIP's floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications and subsequent adaptation of software development tools (e.g. assembler, linker and compiler) are described. Additionally, this work focuses on seamless integration of the co-processor(More)