Gökçe Keskin

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Process variations in advanced CMOS process nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge in circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies(More)
Transistor sizing to control random mismatch is investigated. Input offset voltage of 65 nm bulk CMOS SRAM sense amplifiers are measured to analyze NMOS and PMOS threshold voltage (Vtn, Vtp) variation effects and compare them with statistical models and Pelgrom model predictions. A linear statistical response surface model (RSM) relating input offset to Vtn(More)
An 8-bit, 1.5GS/s flash ADC is presented. Comparators are digitally calibrated using statistical selection. INL of 1.32 LSB and DNL of 1.23 LSB are achieved. Average comparator noise of 5mV<inf>rms</inf> (1.3 LSB) limits SNDR to 37dB at low frequencies. Total power is 35mW, 20mW in the S&amp;H and 15mW in the ADC core. The figure of merit is 0.42pJ/conv,(More)
An active on-chip circuit is demonstrated in 130nm CMOS for the suppression of on-chip power supply noise due to power distribution resonance. Testchip measurement results indicate up to 40% reduction in power supply noise during clock/power gating at a 2% power and 6% area overhead cost. Oscillation time is reduced by 50%. Simulation results show that(More)
Large-scale process variations can significantly limit the practical utility of microelectro-mechanical systems (MEMS) for RF (radio frequency) applications. In this paper we describe a novel technique of adaptive post-silicon tuning to reliably design MEMS filters that are robust to process variations. Our key idea is to implement a number of redundant(More)
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