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This paper presents a new controller validation method for linear multivariable time-invariant models. Classical prediction error system identification methods deliver uncertainty regions which are nonstandard in the robust control literature. Our controller validation criterion computes an upper bound for the worst case performance, measured in terms of(More)
— This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL(More)
The paper proposes a feedforward boundary control to reject measured disturbances for systems modelled by hyperbolic partial differential equations obtained from conservation laws. The controller design is based on frequency domain methods. Perfect rejection of measured perturbations at one boundary is obtained by controlling the other boundary. This result(More)
— in this paper, we describe an architecture of a distributed ADPLL (All Digitall Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni-and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the(More)