We present a CTL model checking algorithm based mainly on forward state traversal, which can check many realistic CTL properties without doing backward state traversal. This algorithm is effective in many situations where backward state traversal is more expensive than forward state traversal. We combine it with BDD-based state traversal techniques using… (More)
Simulation-based verification has both advantages and disadvantages compared with formal verification. Our demand is to find a practical way to verify actual microprocessors. This paper presents an efficient test program generation method for simulation-based verification using techniques developed for formal verification. Our test program generator… (More)
This paper deals with placement and routing techniques for master slice LSIs. The basic idea of both techniques is to make wiring density on the chip more uniform. Algorithms and some experimental results are described.
This paper describes a (special-purpose) logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices. Our system can evaluate a logic circuit containing 4 million logic primitives and 32M bytes of memory at a maximum speed of 800 million active primitive evaluations per second. This… (More)
This paper evaluates the performance of an event-driven logic simulation machine, the SP. Since an event-akiven machine only schedules gates that have signal-changes on their inputs, it processes freer gates than the level-sort machine does. However, if the meti-driven machine spends too many cloch on dynanu " c scheduling, the simulatwn time can not be… (More)
Behavioral simulation is faster than gate-level logic simulation, however, the simulation speed is too slow for large systems. Simulation specific machines accelerated simulation by parallel processing. We developed the method to extract parallelism from behavioral descriptions for fast simulation utilizing these machines. We evaluated our methods utilizing… (More)