Fumiyasu Hirose

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Simulation-based verification has both advantages and disadvantages compared with formal verification. Our demand is to find a practical way to verify actual microprocessors. This paper presents an efficient test program generation method for simulation-based verification using techniques developed for formal verification. Our test program generator(More)
We present a CTL model checking algorithm based mainly on forward state traversal, which can check many realistic CTL properties without doing backward state traversal. This algorithm is effective in many situations where backward state traversal is more expensive than forward state traversal. We combine it with BDD-based state traversal techniques using(More)
For system-level verification of a large-scale design, logic simulation is widely used. When a simulation trace exposes a design error, a designer may rectify the design inadequately because the trace shows only one particular erroneous path. This is one of the essential problems of simulation based verification. On the other hand, model checkers are(More)
This paper describes a (special-purpose) logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices. Our system can evaluate a logic circuit containing 4 million logic primitives and 32M bytes of memory at a maximum speed of 800 million active primitive evaluations per second. This(More)
This paper d i s c u s s e s the test-generat i o n c i r c u i t which automatical ly gene ra t e s a test p a t t e r n f o r a combinational c i r c u i t . The t e s t -gene ra t ion c i r c u i t i s designed so t h a t two algori thms of automatic tes t genera t i o n and f a u l t s imulat ion can be executed by t h e c i r c u i t . The test p a t t(More)