We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
A multi-level 2D-IDWT's architecture with high performance and memory efficiency is proposed. The proposed architecture is composed of two 1D-IDWT cores and one single rearrangement register. Both the 1D-IDWT cores take only one multiplier delay in their critical path at the throughput rate of one-input/one-output. The single register, rather than(More)
Along with the development of semiconductor's channel length that narrows toward the deep submicron and even nanometer, the design of SoC has become increasingly complex. Therefore, how to achieve fault tolerance, aiming to avoid the impact process issues and improve reliability of system, has become the focus of the NoC design. This paper presents a fault(More)
  • 1