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We describe a simple and fast approach to FPGA programming that allows to efficiently exploit the numeric processing capabilities of recent FPGA chips. It basically consists in programming on top of a library of complex components for FPGA based scalable processor networks and providing a high-level programming interface to it. The FPGA application is(More)
This paper introduces a reconfigurable computing cell architecture for pipelined and systolic datapaths in the mixed grained reconfigurable coprocessor array system (MiGCop). The cell is efficiently capable of building scalable parallel-parallel, serial-parallel, and serial-serial signed multipliers. Several cells can be combined to form a reconfigurable(More)
This paper presents a method for embedding arbitrary communication topologies into crossbar interconnection networks. The embedding problem is divided into two parts: first, the placement of the program modules onto the processors, solved by means of quadratic assignment and second, the assignment between logical and physical data channels, solved by means(More)
This paper presents a general architecture for soft processors based on a modified Harvard architecture, SHARF. The separation of instruction and data path is extended by the concept of splitting application and control (address) specific computations. ALUs with any kind of operations and data types can be designed for a SHARF specific controller.(More)