Frederic Neuveux

Learn More
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis(More)
This paper extends the Reconfigurable Shared Scan-in architecture (RSSA) to provide additional ability to change values on the scan configuration signals (scan enable signals) during the scan operation on a per-shift basis. We show that the extra flexibility of reconfiguring the scan chains every shift cycle reduces the number of different configurations(More)
This paper presents a new X-blocking system which allows very high compression and full coverage even if the density of unknown values is very high and varies every shift. Despite the presence of Xs in scan cells, compression can be maximized by using PRPG and MISR structures. Results on industrial designs with various X densities demonstrate consistently(More)
With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are <b>hitting capacity and performance</b> bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper, we address a solution, involving the introduction of test(More)
  • 1