Frans P. M. Beenker

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Testing static random access memories (SRAM's) for all possible failures is not feasible. We have to restrict the class of faults to he considered. This restricted class is called a fault model. A fault model for SRAM's is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms(More)
DOWNLOAD http://bit.ly/1gdyf38 Testing and Testable Design of High-Density Random-Access Memories Testing and Testable Design of High-Density Random-Access Memories deals with the study of fault modeling, testing and testable design of semiconductor random-access memories. It is written primarily for the practising design engineer and the manufacturer of(More)
A method for designing easily testable PLA's with low overhead is presented. The method is based on a reduction of product lines and the addition of a small number of inputs. The required additional hardware is calculated using a statistical cooling algorithm. The presented design-for-testability method guarantees a 100 percent fault coverage with respect(More)