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Several cDNA clones encoding the “33 kDa” protein associated with the photosynthetic water oxidation activity of spinach were sequenced. A 1208 bp insert of one of the clones encodes the entire 331 amino acid residues of the precursor protein including 84 amino acids (8.5 kDa) of the amino-terminal transit peptide, 49 bp of the 5′ and 111 bp of the 3′(More)
In this paper we present a sensor node processor designed to support complex data encryption/decryption operations. The system is developed around an asynchronous processor core supported by AES, ECC and SHA-1 crypto accelerators. The paper describes the chip architecture and its components and gives the chip implementation details. Finally, the power and(More)
The field of lightweight cryptography has developed significantly over recent years and many impressive implementation results have been published. However these results are often concerned with a core computation and when it comes to a real implementation there can be significant hidden overheads. In this paper we consider the case of cryptoGPS and we(More)
In this paper we discuss a theoretical approach to do early assessment of the area and power consumption of hardware accelerators for elliptic curve cryptography. For evaluation we developed several different one clock multipliers as building block for the final serial multipliers. The former are evaluated concerning their efficiency in comparison to(More)
In this paper we describe our own AES implementation, which supports encryption as well as decryption. Our major design goal was to reduce the area while still being capable to support high speed wireless networks such as IEEE 802.11a. Our AES solution provides a throughput of 54MBit/s at 33MHz and requires an area of 0.33mm2 in a 0.25 μm technology. This(More)
Due to asynchronous timing and arbitration asynchronous designs may behave no deterministically. For the test of such systems, this means that an exact timing, i.e. a tester cycle, of a test response cannot be guaranteed. This behavior makes functional tests of asynchronous designs relatively complex or even impossible. Therefore, this paper presents a(More)
Modern, energy-efficient sensor nodes cover a wide variety of application scenarios. For a fast adapting of these devices to new requirements a concurrent development process of software and hardware extensions must be feasible. Here we present a Hybrid Simulation Environment (HSE) that combines a cycle accurate simulator for MSP microcontrollers written in(More)
In this paper we describe a sensor node crypto processor designed for use in wireless sensor networks with strong security demands. The presented system-on-chip is a mixed-signal processor-based design containing the hardware crypto accelerators (AES, ECC, SHA-1) that provide the means for secure communication in the network. The unique system architecture(More)
Even in light-weight wireless computing applications, processing of network-protocols becomes more and more computationand energy-hungry, with increasing data rated and the need for security operations. To cope with such requirements and as alternative to heavyweight computation systems we propose an embedded system that is build for fast network-processing(More)