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This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed(More)
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quality. The System-onChip (SoC) design flow and the changes necessary to successfully implement EDT are presented. Experimental results for three SoC designs targeted for automotive,(More)
Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults − "slow-to-rise" and "slow-to-fall" − are considered as well as delayed(More)
A gate delay test generator for circuits with three-state elements and standard scan-design is presented. The pattern generator combines a well proven stuck-at test pattern generator and a gate delay fault simulator that is used to evaluate the quality of the generated gate delay tests. Experimental results show how the reduced controllability of primary(More)
Short Abstract Most industrial digital circuits contain three-state elements besides pure logic gates. We like to presents a gate delay fault test generator for sequential circuits with standard scan design that can handle three-state elements like bus drivers, transmission gates and pulled busses. The delay test pattern generator is based on a well-proved(More)
Production test is a significant driver of semiconductor manufacturing cost. Test cost is highly influenced by the test concept of a product. This paper gives an overview over the test concept of a complex mobile phone SOC. The particular example is a highly integrated SOC for entry-level mobile phones. The SOC consists, besides digital processing units, of(More)
This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically adapt to and provide excellent performance over a wide range of x-densities. A major contribution of this paper is a(More)
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