Francois Danneville

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This work demonstrates the feasibility of a low area, low consumption, low noise amplifier (LNA) for 40 GHz wireless communications in SiGe:C BiCMOS Technology. The two stage LNA was achieved using a simple approach due to the micro-strip line characteristics and exhibits a gain of 23 dB and 3.7 dB noise figure at 40 GHz for a total DC power consumption(More)
A Fully integrated 283 GHz heterodyne receiver in 65 nm CMOS process is presented in this paper. The circuit includes a resistive differential mixer, an intermediate frequency amplifier and a 282 GHz subharmonic injection locked oscillator. The on-chip oscillator generates a 94 GHz fundamental tone but exploits a 282 GHz third harmonic. An injection signal(More)
This paper presents designs and measurements of distributed amplifiers (DAs) processed on a 130-nm silicon-on-insulator CMOS technology on either standard-resistivity (10 Omegamiddotcm) or high-resistivity (>1 kOmegamiddotcm) substrates, and with either body-contacted (BC) or floating-body (FB) MOSFETs. Investigations have been carried out to assess the(More)
This paper proposes issues in highly accurate high frequency noise simulation for deep submicron MOSFETs. Unlike classical RF design, in which a given device with fixed characteristics is used, CMOS RF design permits selection of user specified device geometries as well as matching elements and bias conditions. Therefore, an exhaustive intrinsic noise(More)
The development of applications in millimeter wave range (mmW) during the last decade is strongly related to continuous progress of Si Technology, which kept on evolving through aggressive transistor gate length down-scaling. In this context, this paper aims to present DC, small signal and noise performance up mmW range of recently developed 45-nm bulk CMOS(More)
This work focuses on the influence of the gate spacer offset width (L<sub>offset</sub>) on SOI MOSFET high frequency (HF) properties. For this purpose, the DC simulated results were calibrated on experimental data of a 130 nm SOI partially depleted technology. Variations of L<sub>offset</sub> were subsequently applied to study its impact on different HF(More)
SUMMARY This paper presents a review of the techniques and models that can be used for the noise performance calculation of active devices under linear and nonlinear operations. In a first part, the modeling techniques and the noise models of FETs, HEMTs, BJTs and HBTs are described. In the second part, a generalization of the impedance field method for the(More)
The behavior of an integrated traveling wave amplifier (TWA), fabricated in a 130 nm silicon-on-insulator (SOI) CMOS process, has been characterized over a temperature range from 25/spl deg/C to 250/spl deg/C. The TWA is a four-stage cascode design which uses floating body (FB) transistors and microstrip lines as passives. A gain of 7 dB with a 0.4-27 GHz(More)
In this paper, we present a set of characteristics (DC, f<inf>t</inf>, f<inf>max</inf>, extrinsic and intrinsic parameters) of a 120 nm gate length InAs/AlSb high electron mobility transistor (HEMT) with a doping plane of Tellurium (Te) operating at room temperature (RT) and low power conditions. A cut-off frequency f<inf>t</inf> equal to 103 GHz has been(More)