Francesco Redaelli

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This work proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. Our approach takes physical constraints of the target device that are relevant for reconfiguration into account. Specifically, we consider the limited number of reconfigurators, which are used to reconfigure the device.(More)
This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solved optimally only by tackling its subproblems jointly, the exceeding complexity of such a task leads to a decomposition into two phases. The partitioning phase is based on a new(More)
Aim of this paper is to define a scheduling of the task graph of an application that minimizes its total execution time on a partially dynamically reconfigurable FPGA. The scheduler has to take into account the reconfiguration overhead of each task, the area constraint of the target FPGA, the precedences between the tasks, configuration prefetching and(More)
The goal of this paper is to introduce a partitioning and floorplanning algorithm tailored for reconfigurable architectures deployable on FPGAs. Our proposed algorithm specifically considers the feasibility of the associated communication infrastructure for a given floorplan. Different from existing approaches, our floorplanning algorithm takes specific(More)
The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. We presented a resource-and configuration-aware floorplacement framework, tailored for Xilinx Virtex 4 and 5 FPGAs, using an objective function based on external wirelength. Our work aims at identifying groups of Reconfigurable Functional(More)
Complex design, targeting System-on-Chip based on recon-figurable architectures, still lacks a generalized methodology allowing both the automatic derivation of a complete system solution able to fit into the final device, and mixed hardware-software solutions, exploiting partial reconfiguration capabilities. The Shining methodology organizes the input(More)
Multi-FPGA systems (MFS’s) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emulation systems. On the other hand, dynamic reconfigurability expands the possibilities of traditional FPGAs by providing them the capability of adapting their functionality while still(More)
The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Recommended by Lionel Torres This work proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. Our approach takes physical constraints of the target device that is(More)
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