Francesco Panicucci

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Improvements in semiconductor nanotechnology have continuously provided a crescent number of faster and smaller per-chip transistors. Consequent classical techniques for boosting performance, such as the increase of clock frequency and the amount of work performed at each clock cycle, can no longer deliver to significant improvement due to energy constrains(More)
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private or shared. As these systems are affected by the wire delay problem, NUCA caches have been proposed to hide the effects of such delay in order to increase performance. A CMP system(More)
Non Uniform Cache Architectures (NUCA) are a novel design paradigm for large last-level on-chip caches which have been introduced to deliver low access latencies in wire-delay dominated environments. Typically, NUCA caches make use of a network-on-chip (NoC) to connect the different sub-banks and the cache controller. This work analyzes how different(More)
The BoulSat Project involves the realization of a bidirec-tional VSAT (satellite connection system) and the study of " poor " a Wireless Metropolitan Area Network (WMAN) to extend the Internet connectivity to the public institutions in the town area. Low-cost or waste materials have been used to build components where possible, thus to make possible for the(More)
We analyze how applications use banks in a large shared CMP L2 D-NUCA cache depending on their locality and we define a power consumption model. Then we develop a mechanism to dynamically turn on and off a bankcluster in order to reduce the energy consumption. Our system is a large shared L2 D-NUCA cache in CMP environment (Figure 1). In this architecture(More)
Current trend of technology scaling makes it possible to put a huge number of transistors on a single die. While dynamic power consumption can benefit from technology scaling, static power consumption get worse, thus making the latter the dominant factor of power consumption in future microprocessor systems. As on-chip cache memories require the most part(More)
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